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PCIe & CXL Microarchitecture & Logic Design - Full Time

Company: Rivos
Location: Mountain View
Posted on: May 27, 2023

Job Description:

Seeking an experienced professional to work on the microarchitecture and RTL design of PCIe and CXL subsystems in a high-performance SoC

  • Evaluation of vendor IP, decision on buy-vs-build for portions of the design
  • Microarchitecture development and specification - from early high-level architectural exploration through micro architectural definition and arriving at a detailed specification
  • Development, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verification
  • Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
  • Design delivery - work with multi-functional engineering teams to implement and validate physical design on the aspects of timing, area, reliability, testability and power Requirements
    • Thorough understanding of PCIe and CXL protocols, including interactions with the System or IO Memory Management Unit
    • Knowledge of on-chip cache coherent memory systems and interconnect
    • 3+ years of direct work experience in microarchitecture and design of subsystems interfacing to PCIe and/or CXL, preferably from the Root Complex
    • Understanding of high performance and low power microarchitecture techniques and trade-offs
    • SystemVerilog or Verilog programming skills
    • Knowledge of logic design principles along with timing and power implications
    • Experience with simulators and waveform debugging tools Education and Experience
      • PhD, Master's Degree or Bachelor's Degree in technical subject area.

Keywords: Rivos, Mountain View , PCIe & CXL Microarchitecture & Logic Design - Full Time, Other , Mountain View, California

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