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ASIC Digital Design Engr, Sr Staff

Company: Synopsys
Location: Mountain View
Posted on: January 24, 2023

Job Description:

ASIC Digital Design Engr, Sr Staff


USA - California - Mountain View/Sunnyvale

Job Description and Requirements

We are looking for a dynamic ASIC Verification Engineer to work as part of the DesignWare Verification team at Synopsys. You will be expected to use SoC ASIC or Custom IC design to specify, design and implement state-of-the-art verification environments for the DesignWare USB family of synthesizable cores. You will work with RTL designers and be part of a team of Verification Engineers.

Key responsibilities:

  • Your role includes definition of verification specifications, test bench infrastructure design and implementation
  • test cases creation, checkers, assertions and coverage implementation based on test plan
  • behavioral modeling, bus functional modeling and verification coverage metrics definition
  • Performing simulation, random and focused stimulus generation and coverage review
  • Contributes to technical reviews
  • Generates documentation for test plans and verification environments.Key Qualifications:
    • BS in EE/CS with 7+ years of related experiences, or MS with 5+ years of experience in developing and debugging complex SoC testbench environments
    • Verification experience and debug skills of IP cores and/or SOC RTL designs
    • Experience in developing System Verilog, UVM, VMM or similar HDL based test environments
    • Experience in developing and implementing test plans, extracting verification metrics, developing BFMs and similar verification components
    • Understanding of USB3.0, USB3.1, USB3.2, USB4 and AMBA protocol
    • Technical experience with assertion-based verification, coverage driven methodology and formal verification
    • Familiarity with C/C++, and a sound background in data structures and algorithms is preferable
    • Impressive communication skills, able to demonstrate research and problem solving skills
    • Perform in a technical leadership roleThe base salary range across the U.S. for this role is between $133,000 to $232,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

      Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

      Job Category



      United States

      Job Subcategory

      ASIC Digital Design

      Hire Type


      Base Salary Range

      $133,000 - $232,000

Keywords: Synopsys, Mountain View , ASIC Digital Design Engr, Sr Staff, Other , Mountain View, California

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