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CPU Performance Modeling Engineer, Staff

Company: Synopsys
Location: Mountain View
Posted on: November 25, 2022

Job Description:






CPU Performance Modeling Engineer, Staff







42256BR





USA - California - Mountain View/Sunnyvale



Job Description and Requirements


Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.


CPU Performance Modeling Engineer, Staff

This role is for the ARC Processor group at Synopsys and will be part of the architecture and design R&D Team. You will explore ways to improve the performance of leading vision and neural network processors including state of the art DSP and control functions. You will leverage your processor architecture, design and performance knowledge to propose enhancements, optimization and features for the next generation based on performance assessment and PPA impact.

Primary Responsibilities

  • Consult with architects to create executable specs by building domain specific functional models (C++) for next generation of ARC processors.
  • Set team direction and propose methodologies towards developing a complete processor architectural functional model by integrating domain specific processor modules using C++ framework.
  • Operate autonomously towards annotating timing/cycle information to functional models to build cycle approximate performance models
  • Correlate performance model results against VCS based RTL simulations
  • Partner with RTL design and Verification teams during the execution phase for formal/dynamic verification
  • Demonstrate leadership in characterizing benchmarks, workloads and use cases (application code) and proposing microarchitectural optimizations for IPC improvements.
  • As part of the largest EDA company, you will be in contact with remote teams on different continents and will work closely with customers located in Asia, Americas and Europe.Keywords: Performance modeling, C++, Architectural functional models, systemC, cycle approximate performance models, FPGA, Verification, ASIC, Linux, Verilog, TCL, Perl or Python

    Must have skills:
    • Masters/Bachelor or above degree in electronic/electrical engineering or computer science
    • 8+ years of ASIC/SoC Performance modeling experience with excellent knowledge of Compute Architecture (Core)
    • Experience with processor / DSP designs, memory hierarchies, cache controllers, arithmetic units
    • Hands on experience on a popular simulation framework or Instruction Set Simulator (Eg. GEM5, Spike, QEMU)
    • Excellent C++ and scripting (shell & python) skills with exposure to SystemC and assembly for test cases
    • Ability to start things from scratch i.e (create a code base from file 0) and ability to infuse code into existing model.
    • Familiar with Industry standard interfaces like AMBA-AXI, AHB
    • Proficient in RTL design and coding with Verilog
    • Familiar with RISC, CISC, VLIW ISA, compilers and debug tools
    • Exceptional debugging and troubleshooting skills
    • Excellent communication skills, teamwork skills and demonstrates autonomy
    • Ability to work simultaneously on multiple tasks
    • Has a proven desire to learn and explore new technologies. Demonstrates good research and problem-solving skills.
    • Networks with internal and external personnel in domains of architecture, design (RTL/Physical) and verificationSynopsys has adopted a COVID-19 vaccination policy to safeguard the health and well-being of our employees and visitors. As a condition of employment, all employees based in the U.S. are required to be fully vaccinated for COVID-19, unless a reasonable accommodation is approved or as otherwise required by law.

      Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.




      Job Category

      Engineering



      Country

      United States



      Job Subcategory

      ASIC Digital Design



      Hire Type

      Employee


Keywords: Synopsys, Mountain View , CPU Performance Modeling Engineer, Staff, Other , Mountain View, California

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