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ASIC Power Architect, Devices and Services

Company: Google Inc.
Location: Mountain View
Posted on: May 3, 2021

Job Description:

Minimum qualifications:

  • BS degree in Electrical Engineering or equivalent practical experience.
  • 5 years of experience in power management or power design/methodology.
  • Experience with ASIC power methodology.

Preferred qualifications:

  • MS/PhD degree in Electronics or Computer Engineering, with emphasis on computer architecture, performance or power analysis.
  • Experience with one or more of the following areas: power modeling, estimation, defining power targets, power management IP and sensors, techniques for power/voltage domain design, droop detection/mitigation and Voltage Frequency Scaling.
  • Experience with one of more of the following areas: modeling and validation in Virtual prototyping and TLM environments, algorithmic development and prototyping software for power management.
  • Knowledge of software and architectural design decisions on power and thermal behavior of the system, such as thermal or peak power mitigation.

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Define power requirements for an ASIC to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
  • Define power targets, identify power scenarios and track IP power.
  • Perform algorithm development, modeling and SW prototyping of power control features.
  • Conduct post-silicon characterization and productization of power features, mitigation strategies.
  • Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.

Keywords: Google Inc., Mountain View , ASIC Power Architect, Devices and Services, Other , Mountain View, California

Click here to apply!

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