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Hardware Development Engineer | FPGA RTL

Company: Aeva
Location: Mountain View
Posted on: May 3, 2021

Job Description:

We are looking for an FPGA Engineer with experience implementing digital signal processing algorithms on FPGAs for complex optoelectronic systemsWhat you'll be doing: Participate in all aspects of the FPGA development process, including FPGA architecture definition, code simulation, RTL development and verification, hardware validation and final testingWhat you have: Solid fundamentals in mathematics, digital signal processing and/or communication systems2-5 years experience writing RTL code in Verilog and/or VHDLExperience with bring-up and debugging new hardware systemsAbility to deliver results in a very fast-moving environmentDesire to learn & implement groundbreaking new hardware technologyAbility to quickly produce thoroughly verified logic modulesNice-to-havesExperience on Xilinx Zynq SoC devicesExperience with High-Level Synthesis tools for FPGAExperience with interfacing JESD204b ADC/DACsKnowledge of FFTs, correlators, polyphase filters, I-Q mixers, etc.Knowledge of advanced verification techniques (transaction-level self-checking test benches, constrained random testing, etc.)What's in it for you: Be part of a fast paced and dynamic teamVery competitive compensation and meaningful stock grantsExceptional benefits: Medical, Dental, Vision, and moreUnlimited PTO: We care about results, not punching timecardsAeva is building the next-generation of sensing and perception for autonomous vehicles and beyond. With its unique ability to measure instantaneous velocity for each pixel, long range performance at high resolutions, while being free from LiDAR or sunlight interference, Aevas 4D LiDAR is built from the ground up at silicon photonics scale for mass market applications.Mountain View, CA /Hardware /Full-TimeSDL2017

Keywords: Aeva, Mountain View , Hardware Development Engineer | FPGA RTL, Other , Mountain View, California

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