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ASIC Sign-off Engineer

Company: Google
Location: Mountain View
Posted on: May 3, 2021

Job Description:

Minimum qualifications: + Bachelor's degree in Electrical Engineering related field or equivalent practical experience with 5 years of industry experience. + Experience in physical verification checks like DRC, LVS, Antenna, ERC, PERC, ESD etc. + Experience in IR/EM analysis tools like Redhawk and/or Voltus. + Scripting experience in Python or Perl or TCL. Preferred qualifications: + Tapeout experience in cutting edge technology nodes + Expertise in sign-off PDV tools like PDK Concepts, Calibre or ICV. + Expert user of PnR tools like ICC/Innovus with regards to physical convergence + Basic device physics and electrical circuit analysis (resistive and RC networks) + Overall understanding of high performance synthesis, PnR and STA optimizations Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step. You will be part of Googles Silicon team, developing high performance and low power hardware to enable Googles continuous innovations in mobile working with our ASIC and SoC teams. You will work with Implementation teams to drive feasibility studies, timely physical verification and power grid signoff convergence for high performance designs including setting up power grid, physical verification flows and methodology to achieve correct by construction design convergence. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. + Develop physical verification methodology aspects of ASIC physical implementation + Converge block, sub-system level physical verification and power grid aspects. + Plan and propose power grid distribution methodology required for high performance and low power designs + Drive improvements in block and sub-system level physical implementation and QOR (power, timing, area). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy (/eeo/) and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form (l/forms/aBt6Pu71i1kzpLHe2) .

Keywords: Google, Mountain View , ASIC Sign-off Engineer, Other , Mountain View, California

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