Physical Design Lead, Static Timing Analysis

Company: Google
Location: Mountain View
Posted on: April 3, 2021

Job Description:

Physical Design Lead, Static Timing Analysis

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 10 years of technical experience in silicon implementation and chip integration.
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation. Preferred qualifications:
  • MS in Electrical Engineering, Computer Science.
  • Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
  • Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
  • Knowledge of semiconductor device physics and transistor characteristics.
  • Delivery of high complexity silicon in state-of-the-art technology process nodes.
  • Ability to lead cross-functional teams. About the job Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step. In this role you will be part of a team responsible for delivering silicon for a range of applications and experiences. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities
    • Lead functional team responsible for delivering system-on-chip (SoC) Static Timing Analysis.
    • Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.--
    • Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area.
    • Own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoC's. Location Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form . To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Keywords: Google, Mountain View , Physical Design Lead, Static Timing Analysis, Other , Mountain View, California