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Senior Hardware Verification Engineer

Company: Aeva, Inc.
Location: Mountain View
Posted on: September 16, 2020

Job Description:

We are looking for a senior-level Verification Engineer with deep expertise in ASIC verification.

What you'll be doing Help define a comprehensive verification methodology for SoCs, including test plan development and review, coverage goals, performance enhancements and regression methodology.

Evaluate tradeoffs in block and full-chip verification, directed and constrained random approaches in a fast paced startup environment.

Leverage and refine automated build and regression flows for complex logic designs. Report and summarize results to team leads.

Verify DSP blocks against bit-accurate C models. Work closely with algorithm team to identify corner cases.

Work closely with design engineers to understand functional safety requirements and how they influence verification.

Share domain-expertise in verification techniques with other verification and design engineers

What you have 10+ years industry experience; including at least one ASIC tapeout

Extensive experience with a variety of verification tools and environments, and a deep understanding of their differences and capabilities to optimize the right methodology with schedules as the top priority.

Proven experience in full chip verification from test plan development to tape-out sign-off.

Experienced in SystemVerilog, UVM, and scripting languages like Python and Tcl.

Expertise in using industry standard simulation tools such as ModelSim, VCS, QuestaSim, etc.

Experience with gate simulations tape-out sign-off criteria

Ability to debug/troubleshoot large designs (needle in a haystack scenarios) comfortably

Proven ability to deliver results in a very fast-moving startup environment, self-driven and a team player.

Eager to learn & implement groundbreaking new hardware technology

knowledge of industry standard interfaces like AXI4

Lab bringup and debug experience, including reproducing system level issues in simulations.

Nice-to-haves Experience with Verilog DPI, C/C++ coding

Familiarity with standard VIPs such as DDR, Ethernet, SPI

Experience with test plan building tools like Vmanager is a plus, but not essential.

What's in it for you Be part of an early start-up that's backed by industry leading venture capitalists

Very competitive compensation and meaningful equity!

401k Matching

Exceptional benefits: Medical, Dental, Vision, and more!

Unlimited PTO: We care about results, not punching timecard

Paid lunches, ping pong tournaments, and fun team off-sites!

Aeva develops a new sensing & perception paradigm for autonomous machines. Aeva's technology brings together the best of vision, depth & motion sensors into a single product with superior performance. Compared to today's best in class, it provides greater range & resolution across weather conditions and a new dimension to precisely measure velocity of every pixel in the scene.

Keywords: Aeva, Inc., Mountain View , Senior Hardware Verification Engineer, Other , Mountain View, California

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