RTL Design Engineer, TPU Chassis
Company: Google
Location: Sunnyvale
Posted on: April 4, 2026
|
|
|
Job Description:
Minimum qualifications: Bachelor's degree in Electrical
Engineering, Computer Engineering, Computer Science, or a related
field, or equivalent practical experience. 1 year of experience
with register-transfer level (RTL) design using Verilog or
SystemVerilog. Preferred qualifications: Master's degree or PhD in
Electrical Engineering, Computer Engineering or Computer Science,
with an emphasis on computer architecture. Experience architecting
RTL solutions. Experience with SOC implementation standards and
interfaces (e.g., AXI). Experience with scripting languages (e.g.,
Tcl, Python or Perl). Experience with CDC, RDC, RTL Linting, and
LEC. Strong understanding of digital design fundamentals, including
synchronous and asynchronous logic, state machines, and bus
protocols. About the job In this role, you’ll work to shape the
future of AI/ML hardware acceleration. You will have an opportunity
to drive cutting-edge TPU (Tensor Processing Unit) technology that
powers Google's most demanding AI/ML applications. You’ll be part
of a team that pushes boundaries, developing custom silicon
solutions that power the future of Google's TPU. You'll contribute
to the innovation behind products loved by millions worldwide, and
leverage your design and verification expertise to verify complex
digital designs, with a specific focus on TPU architecture and its
integration within AI/ML-driven systems. As an RTL Design Engineer
for TPU Chassis, you will join the team at the heart of our
SoC-level architecture. You will drive the design and
implementation of critical top-level systems, including global
communication, CSR, debug, and reset infrastructures. This is a
highly cross-functional leadership role where you will collaborate
with IP and SoC teams to ensure seamless integration and deliver
high-quality RTL to physical design, verification, and firmware
partners through every project milestone. The AI and Infrastructure
team is redefining what’s possible. We empower Google customers
with breakthrough capabilities and insights by delivering AI and
Infrastructure at unparalleled scale, efficiency, reliability and
velocity. Our customers include Googlers, Google Cloud customers,
and billions of Google users worldwide. We're the driving force
behind Google's groundbreaking innovations, empowering the
development of our cutting-edge AI models, delivering unparalleled
computing power to global services, and providing the essential
platforms that enable developers to build the future. From software
to hardware our teams are shaping the future of world-leading
hyperscale computing, with key teams working on the development of
our TPUs, Vertex AI for Google Cloud, Google Global Networking,
Data Center operations, systems research, and much more. The US
base salary range for this full-time position is $117,000-$166,000
bonus equity benefits. Our salary ranges are determined by role,
level, and location. Within the range, individual pay is determined
by work location and additional factors, including job-related
skills, experience, and relevant education or training. Your
recruiter can share more about the specific salary range for your
preferred location during the hiring process. Please note that the
compensation details listed in US role postings reflect the base
salary only, and do not include bonus, equity, or benefits. Learn
more about benefits at Google . Responsibilities Define and
document the microarchitecture for complex digital designs within
the TPU. Write high-quality, performant, and power-efficient
register transfer level (RTL) code, primarily in SystemVerilog.
Collaborate with the Verification team to develop test plans, debug
RTL, and ensure functional correctness. Work closely with the
Physical Design team to meet timing, area, power, and
manufacturability requirements. Contribute to the development and
enhancement of design tools, flows, and methodologies.
Keywords: Google, Mountain View , RTL Design Engineer, TPU Chassis, Engineering , Sunnyvale, California
