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Chip Packaging Engineer

Company: Emonics, LLC
Location: Mountain View
Posted on: January 25, 2023

Job Description:

Candidate Roles and Responsibilities

--- 5+ years' experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD
and SiP package design tools.
--- Creating die and BGA symbols from scratch or from spreadsheet inputs
--- Setting up design environment, including tech files, stack ups, and constraints
--- Setting up Constraint Manager from scratch for complex packages (diff pair creaton, multiple power supplies, net
and zone-specific constraints.
--- Routing signals and matching length both manually and using tool features
--- Design file management and documentation from initiation to final signoff
--- Generation of POD
--- Solid knowledge of top package suppliers design rules and basic manufacturing practices

Desired experience
--- Experience with Cadence Orbit I/O
--- 2.5D interposer design layout experience using Cadence SiP
--- Experience with Virtuoso and/or Innovus for 2.5D interposer design
--- Experience with Synopsys tools for 2.5D interposer design
--- Experience writing and implementing custom scripts in Cadence tools
--- Familiar with Cadence PVS

Keywords: Emonics, LLC, Mountain View , Chip Packaging Engineer, Engineering , Mountain View, California

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