SOC Design Engineer

Company: INTEL
Location: Aptos
Posted on: January 22, 2023

Job Description:

Job Description
We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology. This is a structured ASIC team under Intel's Programmable Solutions Group (PSG) targeting 5G, cloud computing, and high-end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.As a SOC Design Engineer Lead, (senior technical staff )you will use your knowledge of Logic Design, Verification, and FPGA technology to lead pre-silicon verification efforts (including IP, integration, and full-chip aspects), both internal and external, to use the Structured ASIC technology. The position requires a self-driven candidate with deep knowledge in design, verification, and communication interfaces, coupled with good communication skills.Areas of responsibility for this role include, but not limited to the following:

• Be the lead on the overall architecture design, implementation of complex features/flows/protocols, and their interactions with rest of the SoC and with the platform.
• Own verification of IP integration and/or SoC level flows. Lead the development of the design architecture, logic design, verification strategy, requirements, environments, tools, and methodologies.
• Apply your knowledge of design methodologies verification principles and techniques and your judgement to drive the team to write architecture specifications, functional and microarchitecture specifications and realize the corresponding RTL designs.
• Provide debugging test failures to root cause, and recommending solutions.
• Collaborate with cross-functional folks to drive continuous improvement to both the design, verification plans/collateral, and to methodology development -to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
  Qualifications
  Relevant experience can be obtained through work, classes, projects, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
  Education Requirement
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or
  • Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering.
    Minimum Qualifications
    • 7+ years of relevant experience, experience should include:
    • Design experience (RTL Design, definition, etc.)
    • Experience in SDC generation, synthesis,
    • Experience in FPGAs or ASICs, SERDES, and networking applications.
    • Experience in test plan definition and testcase development in C/Assembly/System Verilog.
    • Experience in verifying design at RTL level and gate-level simulation.
    • Experience with scripting languages (e.g., Perl, Python, Shell, etc.)Preferred QualificationsExperience in analog and digital design.
      -
      Inside this Business Group
      The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
      Other Locations
      US,OR,Hillsboro;US,TX,Austin;US,CA,Folsom;US,CA,San Diego;US,CA,San Francisco;US,CA,Santa Clara
      Covid Statement
      Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
      Posting Statement
      All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
      Benefits
      We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
      Annual Salary Range for jobs which could be performed in US, California: $156,410.00-$250,410.00
      *Salary range dependent on a number of factors including location and experience
      Working Model
      This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Keywords: INTEL, Mountain View , SOC Design Engineer, Engineering , Aptos, California