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Synthesis STA Design Engineer

Company: Yoh Services LLC
Location: Mountain View
Posted on: September 19, 2022

Job Description:

Synthesis & STA Design Engineer

We are looking for a Synthesis & STA Engineer to contribute to delivering high standard EFLX (embedded FPGA) and nnMAX (Inference accelerator) cores in advance technology nodes. You will work closely with the Architect, Designer and Implementation team in developing IPs. You will work on setting up flows, writing timing constraints, running synthesis, fixing timing paths, and timing signoff.

We are looking for passionate Engineers that desire to be part of an aggressive, venture-backed startup team that is changing chip architecture. We have an entrepreneurial spirit that is innovative and brings our AI solution to life.

Responsibilities

  • Deploy synthesis and STA flows with industry standard tools
  • Setting up synthesis methodology to optimize design
  • Writing and validating timing constraints
  • Signoff timing closure
  • Generating timing model (LIB) for IPs
  • Develop and validate high performance low power clock network guidelines
  • Generate and Implement ECOs to fix timing, noise
  • Participate in establishing CAD and Design methodologies for correct by construction designs
    Required Experience:
    • 7+ years of Synthesis and Static Timing Analysis experience on IP and/or SOC designs
    • Deep Knowledge about industry standards and practices in Synthesis, including Physically aware synthesis and Static Timing Analysis
    • Power user of industry standard STA & Synthesis tools
    • Hands-on experience in Timing Constraints / SDC
    • Deep understanding of timing corners, operating modes, OCV, cross-talk, noise, signoff criteria
    • Hands-on experience in Logic Equivalency Checking / Formal Verification
    • Familiar with Functional and Timing ECO techniques
    • Familiar with DFT functionality and implementation
    • Shown Knowledge of Basic Architecture and HDL languages like Verilog to be able to work with logic design team for timing fixes
    • Deep Understanding of scripting languages such as Perl/python/Tcl
    • Familiar with digital implementation flows and methodology
    • Bachelors or Master's Degree in EE/CS required
      Preferred Experience
      • Clocking
      • RTL design
      • Physical Design / Implementation
      • Physical Verification
      • Power optimization

        #Dice-SPG

        #Zip-SPG

        #Mon-SPG

        #CB-SPG

        #IND-SPG

Keywords: Yoh Services LLC, Mountain View , Synthesis STA Design Engineer, Engineering , Mountain View, California

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