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UVM/Universal Design Verification Engineer

Company: US Tech Solutions
Location: Mountain View
Posted on: May 10, 2022

Job Description:

US Tech Solutions is seeking a "UVM/Universal Design Verification Engineer " for a 12+ month contract position with a client in Mountain View, CA

UVM/Universal Design Verification Engineer
6+ Months
Mountain View, CA

Design Verification Engineer, The job description may outline various other things however mainly they are looking for someone having direct/enough experience on DV (Design Verification) using the VCS-based UVM methodology .

Project Overview:
A low power digital chip/SOC project built from interval developed IP or some off-the-shelf open source IP and/or third party IP.

Overall Responsibilities:
Digital Design Verification for an SOC project at both IP and system level. Establish DV workflow and build necessary scripting.

Top 3 Daily Responsibilities:
Work closely with the architecture and RTL designers on verifying the functionality correctness of the design.
Reviewing the architecture and design specification. Define test environment and test plans at both IP and chip level.
Execute the test plan, including test development, reference model design, and failure debug, contribute to the development of overall verification infrastructure and tools.

Mandatory Skill/Experience/Education:
Education: Bachelor's degree in Electrical Engineering, or equivalent practical experience.
4+ years experience as verification engineer with SystemVerilog, UVM, and functional coverage.
-Knowledge of digital logic design and verification, CPU/SOC architecture and microarchitecture.
-A big plus, though not required, to have good software skills, including experience with C/C++ for reference model development and enhancement.
Specific Tools or Applications experience (ex. Google Apps, Salesforce CRM, etc):
VCS, Verilator, or other digital simulation tool
Verilog/System Verilog, UVM
Certification or license (ex. CPA, PMP, Cisco): N/A

MS degree in Electrical Engineering, 10+ years of equivalent practical experience.
Exposure to the whole digital design verification life cycle from spec through bring-up.
Experience in design verification techniques including constrained-random simulation, formal property verification or static verification.
Experience with RISC-V CPU verification and formal verification methodology is a plus.
Experience with secure silicon design or verification. Experience working with RTL teams and design integration methodologies that improve team productivity and velocity.

About US Tech Solutions:
Your talent, our opportunities - This is the premise behind US Tech Solutions.
You have the skill we have the opportunity. As a team, we work passionately for you to get the right career opportunity across industry verticals and functions. For past sixteen years, leading Global
Companies and Fortune 500 come to us to get the right talent. Whether you want to work as full-time, contractor or part-time, technical or non-technical our talent consultants will connect with the right career opportunity globally.
Connect with our talent team today.
USTECH was founded in 2000 by Manoj Agarwal. Today, we are a global firm offering talent solutions to 150 customers including 20% of Fortune 500 across Financial Services, Healthcare, Life Sciences, Aerospace, Energy, Retail, Telecom, Technology, Manufacturing, and Engineering. We are headquartered in New Jersey with 40 global locations across the USA, Canada, Europe, and India. Deloitte has recognized USTECH as one of the fastest growing private businesses for the past five consecutive years and INC 500 for the past three. We have also been rated "The Top Business in the US" by Diversity Business since 2011. To learn more about how US Tech Solutions visit our website:

"U.S. Tech Solutions, Inc. is an Affirmative Action, Equal Opportunity Employer. Our employment decisions are made without regard to race, color, religion, gender, national origin, age, disability, marital status, veteran or military status, or any other legally protected status. "

Apply: Interested candidates are requested to send their resume to Ankit Saxena at

Keywords: US Tech Solutions, Mountain View , UVM/Universal Design Verification Engineer, Engineering , Mountain View, California

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