Test Engineer
Company: Altran
Location: Morgan Hill
Posted on: February 25, 2021
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Job Description:
About AltranAltran is the world leader in engineering and
R&D services. We offer our clients a unique value proposition
to meet their transformation and innovation challenges. We support
our clients, from concept through industrialization, to develop the
products and services of tomorrow and have been working for more
than 35 years with major players in many sectors: automotive,
aeronautics, space, defense & naval, rail, infrastructure &
transportation, industrial & consumer products, life sciences,
communications, semiconductor & electronics, software & internet,
finance & public sector. Altran has more than 50,000 employees
operating in over 30 countries. In April 2020, we became part of
Capgemini, a global leader in consulting, digital transformation,
technology and engineering services. Visit us at www.altran.com.DFT
Engineer Qualification/Experience/Skills Required* Ability to
define and describe (write specification for) system architecture,
external interfaces, register definitions and operations, major
partitions* Ability to write clear, concise documents and diagrams
(timing, state machines, register maps, memory organization,
synchronization sequences, etc.) to describe functional and
operational (parametric) aspects of a complex SoC* Domain knowledge
of various software applications and their underlying hardware
requirements (e.g., networking, AI, Machine Learning, storage
devices, IoT)* Experience in Digital module design and
micro-architecture* Experienced at modeling complex state machines,
datapaths and bus protocols/high speed (bandwidth) interfaces such
as PCIe,* 3+ years of hands-on experience with DFT and test flow
with commercial EDA tools (Synopsys, Mentor) for large and complex
SoCs. * Strong fundamental knowledge of DFT techniques include
JTAG, ATPG, test pattern translation, yield learning, logic
diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST.
Experience with Synopsys DFT Complier, Tetramax and VCS is
required. * Experience with TestKompress, Tessent and
Modus/Encounter tool suite is a plus.* Experience in RTL
simulation, synthesis, Linting, CDC checks, STA, DFT, quality
metrics* Hands-on expertise in writing System Verilog and VHDL*
Hands-on in Perl/Tcl/Unix scripting * Excellent analytical, and
problem solving skills* 8+ years' industry experience, Master's
degree or equivalent in EE or Computer Engineering (CE)Roles &
Responsibilities* Write clear, concise specification for an SoC
including functional and timing descriptions for top level
pins/ports/interfaces, registers and memories, state machines,
datapaths, operating modes, exception/error handling, clocking,
reset, power domains, etc.* Describe parametric/operating
environment requirements including performance, power, area (PPA)
targets, temperature and process ranges, IO pads, parametric tests,
etc.* Interact with other system architects to define the
application environment for the SoC being designed (firmware and OS
requirements, external storage devices, sensor/analog components,
etc.)* Provide SoC (top) level constraints and partitions for
RTL/Logic designers, floorplan & PD engineers, DFT requirements*
Perform top/block-level DFT insertion including scan compression,
boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and
pattern simulation. * Verify DFT circuitry and interface with other
blocks, debug timing simulation issues. * Closely work with
physical design team to generate and validate timing constraints. *
Be able to quickly understand problem statements and innovate
solutions for DFT, diagnosis and yield learning. * Be able to work
independently and own the complete task from DFT specification to
final pattern delivery for sub-system and/or SOC.* Working closely
with synthesis, STA, PD and DFT teams to meet all functional
requirements, performance, power and area goals, functional and
diagnostics test coverage* Technical interaction with engineering
teamEducation: B.Tech/B.E., in Electronics/Telecommunication,
Electrical) OR (PG - M.Tech/M.E, in (Electrical,
Electronics/Telecommunication)Please email your resumes at
rashmi.razdan@altran.comThis company is an equal opportunity
employer. All qualified applicants will receive consideration for
employment without regard to race, color, religion, sex, sexual
orientation, gender identity, national origin, disability or
veteran status.
Keywords: Altran, Mountain View , Test Engineer, Engineering , Morgan Hill, California
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